GPU Formal Design Verification Engineer at Prodapt

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate

The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

We're seeking a Formal DV Engineer to take ownership of developing and optimizing formal property verification environments for advanced GPU designs. This technically challenging role emphasizes the construction and debugging of formal verification setups for both new and legacy modules, enabling robust validation of control logic, datapath integrity, and functional properties across complex parallel and memory-heavy architectures. 

Looking for candidates in San Jose, CA or Austin, TX

6 month contract

W2

• Build and refine formal proof environments using SystemVerilog and SVA property development
• Apply sequential equivalence and property-based techniques for block-level and cross-domain feature checking
• Investigate and troubleshoot formal verification failures, updating assumptions, constraints, or collaborating with design teams for root cause resolution
• Integrate C and RTL models for detailed datapath checking, with a focus on convergence and coverage analysis
• Identify and address gaps in coverage by deploying techniques such as abstraction and design minimization
• Act as a liaison for formal methodology enhancements—propose, document, and implement improvements for greater verification efficiency
• Contribute to convergence reporting, complexity documentation, and the regular review of formal feature plans
• Coordinate with architects, designers, and software partners for clarification of design spec and resolution of multi-team issues
• Participate in project management activities via JIRA and Confluence as needed
• Communicate results, technical findings, and progress clearly across engineering and leadership teams

• • Proficient in SV/SVA property and testbench generation
  • Deep familiarity with GPU, CPU, or parallel compute structures, including architectural concepts and functional blocks
  • Prior use of formal tools (e.g., Jasper, VC Formal, Questa Formal) and scripting in Linux
  • Experience with constraint-driven and random verification environments is beneficial
  • Track record of clear communication and teamwork in multidisciplinary engineering organizations