Senior IC Packaging Designer bei Falcomm

Description

Are you passionate about advancing semiconductor technologies and enabling next-generation wireless systems? At Falcomm, we are transforming innovative semiconductor research into real-world solutions through high-performance, energy-efficient RF power amplifier technologies. Our mission is to deliver cutting-edge wireless solutions that push the boundaries of performance, efficiency, and integration.

Falcomm is seeking an IC Packaging Designer to support the development and implementation of advanced semiconductor packaging solutions for RF integrated circuits. This role will focus on designing and optimizing package architectures that support high-frequency performance, thermal efficiency, and manufacturability. The position requires close collaboration with RFIC designers, layout engineers, testing teams, and manufacturing partners to ensure successful integration of silicon, GaN, or III-V MMICs devices into production-ready packages.

Responsibilities:

• Design and develop RFIC packages and substrates optimized for high-frequency performance, including laminate, ceramic, or leadframe-based packages.
• Create package layouts, bond diagrams, and substrate routing using semiconductor packaging EDA tools.
• Work with signal integrity, EM, and thermal simulation teams to validate package performance.
• Generate package documentation, fabrication drawings, and assembly specifications.
• Participate in design reviews, prototype builds, and failure analysis to improve RF performance and yield.
• Collaborate with RFIC designers to co-optimize chip and package performance, minimizing parasitics and signal loss.
• Support package integration with PCB design teams to ensure optimal RF performance at the system level.
• Coordinate with fabrication and assembly partners.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
• 3-5 years of experience designing advanced RFIC semiconductor packages up to 50GHz (e.g., wirebond, flip-chip, PoP, or SiP) using tools such as Cadence Allegro APD/SiP or Mentor Xpedition.
• Strong foundation in electrical, thermal, materials, or mechanical engineering principles relevant to IC packaging.
• Must be willing to work full-time, onsite, in Atlanta, GA.

Preferred Skills:

• Familiarity with signal and power integrity analysis tools (e.g., HFSS, Q3D, PowerSI) and understanding of high-speed interface requirements such as DDR or PCIe.
• Knowledge of substrate manufacturing processes, package layout constraints, and design verification tools including CAM350, Valor, or Calibre.
• Experience with RFIC or 5G packaging design, along with scripting or automation skills (Python, TCL, Perl, or shell) to support design workflows.
• Ability to build accurate 3-D models of packages using Ansys Electronics Desktop and EM-simulate them in HFSS and run thermal simulations on them with Icepak

Benefits

• Competitive Salary and Equity Package
• Comprehensive Health, Dental, and Vision Insurance
• 401(k) Retirement Plan
• Paid Time Off (PTO) and Sick Leave

Disclosure:

• Falcomm is an Equal Opportunity Employer; employment with Falcomm is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
• Applicants wishing to view a copy of Falcomm’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify Falcomm.
• To conform to U.S. Government export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.