Lead E/E & Semiconductor Engineer - SOC Design Verification Engineer bei Capgemini Engineering

%3Ch4%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EJob Description:%3C/span%3E%3C/span%3E%3C/h4%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EWe are seeking a%26nbsp;SoC Design Verification Engineer%26nbsp;to join our team%26nbsp;100% onsite%26nbsp;in either%26nbsp;Seattle, WA%26nbsp;or%26nbsp;Santa Clara, CA. The ideal candidate will be responsible for defining and implementing SoC verification plans, building verification test benches for sub-system/SoC-level verification, and developing functional tests based on the verification plan.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Ch3%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EKey Responsibilities:%3C/span%3E%3C/span%3E%3C/h3%3E%0A%3Cul%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EDrive design verification to closure based on defined verification metrics, including test plan execution, functional coverage, and code coverage.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EDebug, root-cause, and resolve functional failures in collaboration with the design team.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EWork closely with cross-functional teams such as Design, Modeling, Emulation, and Silicon Validation to ensure the highest design quality.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ELead and contribute to continuous improvements in design verification using the latest industry methodologies, tools, and technologies.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3C/ul%3E%0A%3Ch3%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ERequired Skills:%26nbsp;%3C/span%3E%3C/span%3E%3C/h3%3E%0A%3Cul%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EProven track record of%26nbsp;first-pass success%26nbsp;in ASIC development cycles.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EBachelor%26rsquo;s degree in%26nbsp;Computer Science,%26nbsp;Computer Engineering, or a related technical field, or equivalent practical experience.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EStrong experience with%26nbsp;ARM processor-based SoCs%26nbsp;and%26nbsp;AMBA protocols%26nbsp;(AHB, AXI).%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3E8 to 10 years%26nbsp;of hands-on experience with%26nbsp;SystemVerilog%26nbsp;and%26nbsp;UVM methodology.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EProficiency in one or more of the following areas in addition to functional verification:%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cul%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ESystemVerilog Assertions (SVA)%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EFormal Verification%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EEmulation%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3C/ul%3E%0A%3C/li%3E%0A%3Cli%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EExperience with%26nbsp;EDA tools%26nbsp;and scripting languages such as%26nbsp;Python, TCL, Perl, and Shell%26nbsp;for building tools and verification flows.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3C/li%3E%0A%3C/ul%3E%0A%3Ch3%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EPreferred Qualifications%3C/span%3E%3C/span%3E%3C/h3%3E%0A%3Cul%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EExperience verifying%26nbsp;GPU/CPU designs%26nbsp;and developing%26nbsp;UVM-based verification environments from scratch.%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EBackground in design verification for%26nbsp;data center applications, including%26nbsp;Video,%26nbsp;AI/ML, and%26nbsp;Networking.%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EFamiliarity with version control systems such as%26nbsp;Mercurial (Hg),%26nbsp;Git, or%26nbsp;SVN.%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EExperience with IP or integration verification of%26nbsp;high-speed interfaces%26nbsp;such as%26nbsp;PCIe,%26nbsp;DDR, and%26nbsp;Ethernet.%3C/span%3E%3C/span%3E%3C/li%3E%0A%3C/ul%3E%0A%3Ch4%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ELife at Capgemini%3C/span%3E%3C/span%3E%3C/h4%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ECapgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:%26nbsp;%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cul%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EFlexible work%26nbsp;%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EHealthcare including dental, vision, mental health, and well-being programs%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EFinancial well-being programs such as 401(k) and Employee Share Ownership Plan%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EPaid time off and paid holidays%26nbsp;%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EPaid parental leave%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EFamily building benefits like adoption assistance, surrogacy, and cryopreservation%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ESocial well-being benefits like subsidized back-up child/elder care and tutoring%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EMentoring, coaching and learning programs%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EEmployee Resource Groups%26nbsp;%3C/span%3E%3C/span%3E%3C/li%3E%0A%3Cli%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EDisaster Relief%26nbsp;%3C/span%3E%3C/span%3E%3C/li%3E%0A%3C/ul%3E%0A%3Ch4 style=%22margin-bottom: 11px;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3E%3Cspan style=%22line-height: 107%;%22%3E%3Cb%3EAbout Capgemini Engineering%3C/b%3E%3C/span%3E%3C/span%3E%3C/span%3E%3C/h4%3E%0A%3Cp style=%22margin-bottom: 11px; font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3E%3Cspan style=%22line-height: 107%;%22%3EWorld leader in engineering and R%26amp;D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure %26amp; Transportation, Energy, Utilities %26amp; Chemicals, Life Sciences, Communications, Semiconductor %26amp; Electronics, Industrial %26amp; Consumer, Software %26amp; Internet.%26nbsp;%3C/span%3E%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22margin-bottom: 11px; font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3E%3Cspan style=%22line-height: 107%;%22%3ECapgemini Engineering is an integral part of the Capgemini Group, a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided every day by its purpose of unleashing human energy through technology for an inclusive and sustainable future. %3Cspan style=%22line-height: 107%;%22%3EIt is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2023 global revenues of %26euro;22.5 billion.%3C/span%3E%3C/span%3E%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3E%3Cspan style=%22line-height: 107%;%22%3EGet the Future You Want%26nbsp;|%26nbsp;%3Ca href=%22https://www.capgemini.com%22 style=%22color: #0563c1; text-decoration: underline;%22%3Ewww.capgemini.com%3C/a%3E%3C/span%3E%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3E%3Cstrong%3EDisclaimer%3C/strong%3E%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ECapgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EThis is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.%26nbsp;%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3ECapgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EClick the following link for more information on your rights as an Applicant %3Ca href=%22http://www.capgemini.com/resources/equal-employment-opportunity-is-the-law%22%3Ehttp://www.capgemini.com/resources/equal-employment-opportunity-is-the-law%3C/a%3E%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EPlease be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.%3C/span%3E%3C/span%3E%3C/p%3E%0A%3Cp style=%22font-family: Arial;%22%3E%3Cspan style=%22font-size: 12px;%22%3E%3Cspan style=%22font-family: arial, helvetica, sans-serif;%22%3EApplicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.%3C/span%3E%3C/span%3E%3C/p%3E Jetzt bewerben