- Senior
- Optionales Büro in Torrance
Claros is a power management solutions company that is innovating at the intersection of power and compute to make AI more sustainable and widely available. By driving down the cost and complexity of power delivery and leveraging innovative hardware and software, the company seeks to decrease energy consumption, optimize power delivery, increase compute performance, and maximize the efficiency of AI operations.
Sr. CMOS IC Layout Engineer (Contractor)
Contract: 3 - 6 Months
Location: Torrance CA, Hybrid (3 days a week)
Competitive hourly rate: $80-$100 per hour
About Claros
Claros enables Grid-to-Chip power infrastructure solutions for next generation Data Centers. Our mission is to transform power management to meet the global energy demand created by big data, artificial intelligence and ML. Through our innovative power delivery platform, our technology helps next generation data centers implement and operate server platforms that identify, control, and optimize power and energy management systems to meet real-world end user demands. We serve government and commercial customers.
About The Team
We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking. Our response is never “no, but….” instead “yes, if….”. We are mindful of our personal and organizational blinders and try to build an environment where our team members are At Their Best.
About The Role
Claros Technologies is seeking highly skilled, self-motivated Senior Analog IC Layout Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering PMICs (Voltage Regulators, LDO’s, DC-DC Buck Converters), ADC/DAC, PLL etc. As a Senior IC Layout Engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging sophisticated tools.
What You Will Do
- As a Senior Layout Engineers, your responsibilities include crafting layouts for mixed-signal and analog circuits, top-level IC floor planning, chip integration, mask preparation, and collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.
- Work closely with circuit designers to complete the physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in cutting-edge process technologies (55nm down to 12nm (FinFET).
- Use problem solving skills, experience, and creativity to layout circuits that meet size, schedule, and performance specifications.
- Interpretation of LVS, DRC, and ERC reports is key to finding the fastest way to complete the layout, exceeding engineering specifications and expectations. Run physical design verification tools to debug, improve, and verify layout blocks.
- Collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.
What You Bring
- Associates or higher degree with 8+ years of relevant experience in Electronic/IC layout CAD specialization or related program. Demonstrated working Silicon in BCD and advanced CMOS technologies
- Experience in the layout of ADCs, DACs, PLLs, LDOs, Bandgaps, Switch caps, DC-DC Buck Converters
- 2+ years’ experience in IC layout design in FinFET technology node.
- Must be knowledgeable with CAD tools like Cadence Virtuoso XL, PVS/Calibre.
- Proficient at debugging/fixing LVS/DRC errors.
- Experience in leading the tape-out process and working with the foundry for mask making
- Strong understanding of Analog circuit layout fundamentals and best practices.
- Device matching
- Routing flow and shielding for analog signals, logic signals, biases, clocks
- Area estimation
- Power flow
- Signal flow
- ESD electrical and spacing requirements
- Solid understanding of semiconductor manufacturing process and DFM techniques.
- Experience creating an IC floor plan for a mixed-signal ICs
- Experience with synthesis/advanced place & route tools (Innovus).
- Experience is doing IR drop analysis (knowledge in using Cadence tool VOLTUS)
- Understanding of thermal considerations, latchup, ESD, noise, substrate injection, parasitic extractions and optimized power routing
- Experience in providing Bond diagrams for IC packaging
- Must be familiar with Cadence Design Environment (CDE) and Unix OS.
- Programming knowledge in SKILL is a plus.
- Must have strong communication skills and be a team player.
- Ability to effectively prioritize and execute tasks in a high-pressure environment
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