- Professional
- Optionales Büro in Hyderabad
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Role : Lead Design Engineer, Digital Physical Desing
- Responsibilities
- Block level Netlist to GDS delivery
- Subsystem level floorplan, PnR and timing closure
- FCFP/FCI/FCT activities - Full Chip Floor planning, Full chip Integration, Full Chip timing
- Leading/Guiding a team of 2-3 Engineers
- Required Skills
- 5+ years of experience in PnR and STA
- Handson experience in RTL/Netlist to GDS delivery of blocks
- Good understanding of DFT stitching and clock tree strategies
- Strong at density and congestion issues resolution
- Complex blocks floorplan, PnR and STA such as DDRIP. PCIE IP
- Capable of doing PV and IREM fixes along with the timing
- Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
- TCL and PERL scripting knowledge and experience in writing the scripts
- Good exposure to Cadence EDA tool set needed for PD
- Optional Skills
- Handson experience in low power designs
- Handson experience on subsystem level activities
- Flat Chip or small hier chip FC activities
- Complex IP integration like DDR and PCIe
- Experience in guiding freshers/interns
