SoC Performance Architect – Intern (Summer 2026) chez Cadence

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SoC Performance Architect – Intern

Location – San Jose

Summary

As part of the System Architecture team, you will help drive cutting-edge solutions for chiplet based SoCs by building cycle-level performance models for various Cadence IPs (including NoC, NPU, Memory Controller, UCIe), integrating IP models to build chiplet based systems and identifying architectures that maximizes key performance indicators.

Responsibilities

• Develop cycle-level C++/SystemC performance models
• Perform architectural exploration and quantify system performance for different workloads (traffic generators, CPUs, GPUs) and benchmarks - datacenters, AI inference, automotive, applications
• Collaborate with system and IP architects to translate findings into practical solutions that can influence the design and application of chiplet technology

Required Skills

• Currently pursuing BS or MS in electrical/Computer Engineering or equivalent
• Strong coding skills in C++/SystemC, python and similar programming languages
• In depth understanding of computer architecture and memory hierarchy
• Understand modeling concepts – cycle-level/cycle-accurate/event-driven
• Experience developing models for components such as CPU, NoC, GPU, MMU, Caches, memory controllers

Additional Skills

• Experience working with a full system performance simulator like GEM5, or similar
• Knowledge of memory controllers and memory protocols – DDR, LPDDR, HBM, etc
• Experience working with performance benchmarks – SPEC, STREAM, accelerator workloads, generating synthetic traffic representing real traffic
• Understand RTL-Verilog, SV, UVM and experience with performance verification

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