ASIC Designer chez Syntronic

Job Description We are seeking a Senior ASIC Designer to join our hardware engineering team and drive the development of next-generation semiconductor solutions. In this role, you will take ownership of the design, verification, and optimization of complex ASICs, from high-level architectural specifications through implementation and silicon validation. You will influence design decisions across multiple blocks, collaborate with cross-functional teams in architecture, physical design, and verification, and ensure designs meet the most stringent requirements for performance, power, and area. This role is ideal for a highly experienced designer with a proven track record of delivering high-quality silicon and mentoring peers in best practices.

What you'll do

Lead the development of RTL designs using Verilog/VHDL/SystemVerilog based on architectural and functional specifications.

Perform and oversee functional verification at block- and system-level, including simulation, advanced testbench creation, and debugging complex issues.

Execute synthesis, place-and-route, and static timing analysis (STA) to ensure timing closure across multiple design blocks.

Drive design optimization for PPA (power, performance, area), analyzing trade-offs and implementing improvements that impact system-level performance.

Integrate and validate third-party IP, ensuring correct functionality, timing closure, and seamless integration into complex systems.

Collaborate closely with physical design, DFT, and verification teams to resolve timing, DRC, LVS, and post-silicon issues.

Provide guidance and mentorship to junior ASIC designers on RTL coding, verification strategies, and design best practices.

Lead efforts in chip bring-up, silicon debug, and post-silicon validation, identifying root causes and long-term solutions.

Maintain comprehensive documentation of design specifications, verification plans, and implementation results to ensure knowledge transfer and traceability.

What you'll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline.

10+ years of hands-on ASIC design experience, with a track record of delivering complex, high-performance silicon.

Deep expertise in digital design principles including synchronous design, pipelining, clocking, and reset strategies.

Mastery of Verilog, VHDL, and/or SystemVerilog for RTL design and verification.

Extensive experience with industry-standard EDA tools (Synopsys Design Compiler, Cadence Genus/Innovus, Mentor Questa, etc.).

Proven ability to close timing, optimize designs for low power, and resolve challenging PPA trade-offs.

Strong understanding of DFT concepts including scan chains, ATPG, and memory BIST.

Proficiency in scripting languages (Python, Perl, TCL, etc.) to automate design and verification flows.

Exceptional debugging skills with waveform viewers, formal verification, emulation, and prototyping platforms.

Demonstrated ability to lead technical discussions, make architecture-level decisions, and mentor peers.

What will make us REALLY love you

Experience with advanced process technologies (7nm, 5nm, FinFET) and complex system-on-chip (SoC) design.

Familiarity with hardware/software co-design and system-level performance modeling.

Knowledge of high-speed interface protocols (PCIe, DDR, Ethernet, SerDes) and advanced timing closure techniques.

Exposure to mixed-signal integration, FPGA prototyping, and silicon bring-up.

Contributions to open-source EDA tools, verification frameworks, or industry standards.

Strong leadership in guiding junior engineers, influencing design methodology, and fostering cross-functional collaboration.

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