Mixed-Signal Verification Engineer presso Apple

Role Number: 200662891-3543

Summary

Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level. All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.

Description

In this highly visible role, you will be at the center of a wireless Mixed-Signal silicon design group, with a critical impact on getting innovative and functional products to hundreds of millions of customers quickly.

As a Mixed Signal Design Verification Engineer, you will be responsible for the verification of RF and mixed-signal blocks and their interfaces within the wireless SoC. You will interact with the analog/RF design team, digital DV team digital design team, and wireless system team to develop best-in-class verification methodologies that ensure silicon-correct functionality with optimal coverage and time-to-tapeout trade-off.

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience

• Industry verification experience with RF/Mixed-Signal blocks and SOCs

• Expertise building Mixed-Signal testbenches, checkers and tests using System Verilog

• Experience in UVM methodology and HDL (System Verilog, Verilog) for verification

• Strong verification skills in problem solving, testing, and debugging

• Understanding of common analog/RF blocks

• Experience with UPF, Python or Matlab a plus

• Experience with Virtuoso Composer, ADE, and HED also a plus

Preferred Qualifications

• Masters or PhD degree in technical disciplines with at least 5+ years of hands-on experience in specifically

• Mixed-Signal verification

• Wireless experience is a plus

• Expertise creating and using real-numbered analog behavioral models in System Verilog a plus.

• Ability to work well in a team and be productive under aggressive schedule

• Excellent communication skills, self-motivation/organization and the desire to take diverse challenges.