- Junior
- Optionales Büro in Bengaluru
Job Details:
Job Description:
Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Creates prototypes, simulates models, and specifies systems requirements. Prepares and designs logic diagrams and codes for implementing system design and test specifications. Delivers software models for device level bring up, including user visible functionality, timing, and power. Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Qualifications:
Education Requirements:
- Bachelor's degree in computer engineering, electrical Engineering or related field.
Minimum Qualifications
2+ years of relevant experience in the following areas if BS degree
- Experience with CPU based SoC designs processor based SoC architectures.
- Experience with NoC design and integration with AMBA interconnect protocols
- Working experience with peripheral IPs such as USB, Ethernet, I3C.
- RTL developer using ASIC development techniques and designs flows at modern technology nodes including synthesis and timing closure
- Understanding of clock, debug, security, low power methodologies at the SoC level.
- Digital Design experience
- Experience with scripting languages (e.g., Python or Perl).
Preferred Requirements:
- Master's degree in computer engineering, Electrical Engineering or related field.
- Digital design involving multiple clock domains and clock, power management.
- Low power design, tools and methodologies. Power intent UPF specifications.
