Hybrid Sr Chip Design Engineer (London, GB, EC4R 9AF) bei Qualitest

Senior Chip Designer (ASIC / RTL): 

Minimum qualifications:

• Bachelor's degree or equivalent practical experience.
• Experience architecting networking Blocks/ASICs from specification to fully verify delivery.
• Experience working with design networking like: packet processing and system design principles for low latency, high throughput, security, and reliability.
• Experience developing RTL for ASIC subsystems.
• Experience in micro-architecture, design, verification. Logic synthesis, and timing closure is an advantage

Preferred qualifications:

• Networking logic design expertise, including data path IPs and third-party IPs (e.g., SerDes, PCS, MAC).
• Deep understanding of networking protocols and principles (e.g., TCP, IP, Ethernet, PCIe).
• Proven ability to optimize hardware/software interfaces through collaboration with software teams.
• Experience in Micro Architecture of networking solutions such as switches, NICs and endpoints.
• [Optional] Proficiency in a procedural programming language (e.g., C++, Python, Go).
• Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.