Analog Layout Engineer en Weekday AI

Description

This role is for one of the Weekday's clients

Salary range: Rs 1500000 - Rs 4500000 (ie INR 15-45 LPA)

Experience: 4+ yrs

Location: Bangalore, Hyderabad, Germany

Job Type: Full-Time

We are looking for an experienced Analog Layout Engineer with strong expertise in full-custom analog and mixed-signal layout design for advanced semiconductor technologies. This role involves developing high-quality layouts from schematic to GDSII while working closely with circuit designers to optimize performance, area, reliability, and manufacturability. The ideal candidate will have hands-on experience with advanced process nodes, physical verification, parasitic extraction, and layout optimization techniques to ensure first-pass silicon success.

Requirements

Key Responsibilities

• Develop high-quality full-custom layouts for analog and mixed-signal IPs from schematic through GDSII implementation.
• Execute advanced analog layout techniques including common centroid, symmetry, interdigitation, device matching, shielding, guard rings, and noise isolation.
• Perform floorplanning, routing, and layout optimization to achieve optimal performance, power, area, and manufacturability.
• Resolve DRC, LVS, ERC, antenna, density, and latch-up violations to ensure clean physical verification and tape-out readiness.
• Perform parasitic extraction and support post-layout simulation to validate circuit performance.
• Collaborate closely with circuit designers to optimize layouts for matching accuracy, signal integrity, noise reduction, and overall reliability.
• Support tape-out activities, silicon bring-up, and debugging during post-silicon validation.
• Coordinate with CAD and PDK teams to implement process updates and improve layout methodologies.
• Review layouts, mentor junior engineers, and promote layout best practices across the engineering team.
• Contribute to continuous improvements in layout quality, productivity, and design automation processes.

What Makes You a Great Fit

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
• 4–10 years of hands-on experience in full-custom Analog and Mixed-Signal Layout Design.
• Strong expertise in layout optimization techniques including common centroid, interdigitation, symmetry, shielding, guard rings, and matching-sensitive layouts.
• Experience working with advanced semiconductor process nodes such as TSMC 3nm, 5nm, 6nm, 7nm, 12nm, or similar technologies.
• Strong understanding of physical verification methodologies including DRC, LVS, ERC, antenna, density, latch-up, and parasitic extraction.
• Hands-on experience with industry-standard EDA tools such as Cadence Virtuoso Layout XL, Calibre, Virtuoso ADE, StarRC, Quantus, and related verification tools.
• Good understanding of analog circuit blocks including PLL, LDO, ADC, DAC, Bandgap, SerDes, SRAM, IO, PMIC, and other mixed-signal IPs.
• Familiarity with ESD-aware layout practices, reliability analysis, and post-layout verification techniques.
• Strong analytical, debugging, and problem-solving skills with the ability to optimize layouts for performance and manufacturability.
• Excellent communication and collaboration skills with the ability to work effectively across cross-functional engineering teams and mentor junior layout engineers.