Mixed Signal Modeling & Verification Engineer en Cirrus

We are seeking creative and hardworking engineers to join our outstanding Analog/Mixed-Signal Verification team. You will collaborate with systems and design teams to facilitate top down design methodology. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. This position will play a vital role streamlining development methodology for our organization. We are proud of our outstanding environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!

Responsibilities:

Collaborate with multi-functional teams to streamline chip-level integration

You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs

Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS

Develop test plans, test benches, and verification methodologies to verify the microarchitecture and design

Performing regression debug support and other flow/infrastructure development

Independent Interpretation of analog circuit schematics into abstract models

Collaborate with system architects and designers to streamline architectural exploration of next-generation IP

Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow

Required Skills and Qualifications:

MS or higher in Electrical Engineering or Computer Engineering

Experience in development of mixed-signal products

Strong background in analog integrated circuit design

Strong background in System Verilog for real number modeling (RNM) modeling, test bench development & verification

Solid understanding and hands on experience on the design of mixed signal designs

Organized and detailed with strong communication skills

Possess outstanding analytical and problem-solving skills

Hard-working and ability to operate in dynamic environment

Proficient in use of AMS simulators

Preferred Skills and Qualifications:

Python skills would be highly desirable

Teaming closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post-silicon validation efforts

Knowledge of signal processing and System Verilog Assertions and PSL Assertions

Ability to create, evaluate, debug, and improve a verification process

Opportunity to mentor junior engineers in verification methodology

UVM experience would be highly desirable

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