Design Engineer - STA na Silabs

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Who We Are
Silicon Labs is a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, and robust ecosystem enable developers to solve complex wireless challenges with ease. We hire the most innovative talent to solve the industry’s toughest problems and deliver cutting-edge solutions across IoT, infrastructure, automotive, and consumer markets.

What You’ll Do
As a Static Timing Analysis (STA) Engineer, you will be responsible for timing sign-off of high-performance SoCs and ASICs. You’ll work closely with cross-functional teams to ensure timing closure across various operating modes and process corners.
Responsibilities:

• Own STA execution for digital blocks or top-level designs
• Develop and validate SDC constraints for RTL-to-GDSII flow
• Analyze setup/hold violations and collaborate with RTL, synthesis, and physical design teams
• Generate and interpret timing reports using industry-standard tools
• Implement timing ECOs to resolve critical path issues
• Contribute to timing methodology improvements and automation
• Perform timing checks for CDC, false paths, and multicycle paths

What You Need
Required Qualifications:

• 2–4 years of experience in STA for ASIC or SoC development
• Strong understanding of timing fundamentals including PVT variations and clocking schemes
• Proficiency with tools like Synopsys PrimeTime or Cadence Tempus
• Experience in writing and debugging SDC constraints
• Scripting skills in TCL, Perl, or Python
• Exposure to synthesis, floorplanning, and physical design flows
• Strong analytical and communication skills

Education:

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields

Benefits & Perks :

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Equity Rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.