Verification & Emulation Methodology Engineer na Celestial AI
Celestial AI · Santa Clara, Estados Unidos Da América · Onsite
- Professional
- Escritório em Santa Clara
About Celestial AI
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
ABOUT THE ROLE
Celestial AI is looking for a Verification & Emulation Methodology Engineer who thrives on both building methodology and using it daily. In this role you will:
- Contribute directly to block- and system-level verification in SystemVerilog/UVM, driving coverage and closing bugs.
- Build and scale the automation and infrastructure that enables the entire team to be more effective.
Because we are a startup, you will split your time between hands-on DV work (tests, debug, coverage closure) and methodology development (regressions, dashboards, CI, emulation flows). We believe the best methodology is created by those who actively use it.
This is a rare opportunity to both shape modern verification infrastructure and apply it on cutting-edge photonic AI hardware with minimal legacy constraints.
ESSENTIAL DUTIES AND RESPONSIBILITIES
- Regression Platform: Design, maintain, and scale end-to-end regression infrastructure while also running hands-on regressions for your verification tasks.
- Coverage Methodology: Develop and apply robust coverage flows, ensuring meaningful analytics and closure.
- Emulation Flow Development: Create and use emulation flows for HW/SW co-verification, performance validation, and debug acceleration.
- Dashboards & Insights: Build visualization and alerts to track regressions and coverage.
- Cross-Functional Partnership: Work closely with design and DV teams to codify best practices, debug efficiently, and perform root-cause analysis; collaborate with platform/IT teams operating CI and the compute farm.
- Innovation & Evaluation: Pilot new tools and techniques to improve performance, observability, cost, and throughput, while grounding proposals in your own verification experience.
QUALIFICATIONS
- Bachelor’s in Computer/Electrical Engineering, Computer Science, or related field and 5+ years of experience; or Master’s and 3+ years of experience.
- Proven background in verification or EDA methodology development for ASIC/SoC programs.
- Strong scripting/software skills: Python and Linux shell required; Comfortable with packaging, testing, and code quality for internal tools.
- Familiarity with industry simulators and emulators (e.g., Cadence Xcelium, Synopsys VCS, Siemens Questa; and emulation platforms such as Palladium/Protium, ZeBu, or Veloce).
- Working knowledge of SystemVerilog/UVM concepts sufficient to instrument flows and reason about coverage/testbench structure (deep DV expertise a plus).
LOCATION: Santa Clara, CA
For California Location:
As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
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