Hybrid Design Engineer II bei Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

What we are looking for : 
 
Minimum Qualifications:
•            2-7 years (with Btech) or 5 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
•            Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
•            Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
 
Preferred Qualifications:
•            Experience in PCIe/UCIe LTSSM states is a plus.
•            1-2 years of experience in FPGA Design and Schematic design is a plus.
•            1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
•            Familiarity with Verilog RTL coding for FPGA, python,C/C++
•            Good communication skills 
•            Candidates are expected to be passionate about analog and digital electronic circuit design.
 

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