- Junior
- Optionales Büro in San Jose
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Detailed understanding of physical design automation flow and EDA tool functions.
- Running EDA tools in each technical area to qualify the flow automation and QA.
- Generating feedback for bug fixes and enhancements.
- Developing documentation for knowledge sharing and training.
- Tracking project schedules and documenting all phases of work.
Skill Requirements:
- Understanding of ASIC design flow. Good knowledge of physical design automation flow, Tcl or Perl scripting , MS Office.
- VLSI design experience. RTL design using Verilog HDL is preferred.
- Good trouble-shooting skills.
Education Requirements:
- BS or above